In the area of high-performance computing (HPC), parallel processor architectures (multi- and many-core processors, and Graphics Pocessing Units - GPUs) have been increasingly used in the last few years since no performance increase could be achieved any more by higher clock frequencies. However, these solutions based on many single processor kernels come with a large chip area and a high power consumption.
On the other hand, programmable hardware in the form of FPGAs (Field-Programmable Gate Arrays) is also used for HPC applications since FPGAs allow massively parallel processing without the overhead of complete processor kernels. But processing floating-point data as required in most HPC applications is problematic on FPGAs. Only a limited number of floating-point units (FPUs) can be realized on an FPGA by combining simpler components. The same limitation also holds for coarse-grained reconfigurable arrays (CGRAs) which are – as opposed to FPGAs – based on processing units for data words (e.g. 32 bit words). This makes them in principle better suited for executing numerical algorithms. But almost all CGRAs developed so far contain only units for processing integer or fixed-point data. CGRAs extended by FPUs are a promising option for computation-intensive algorithms, e.g. in the domains of scientific computing or 3D graphics. This extension will be researched and evaluated in the HiPReP project.
First, suitable HPC benchmark program kernels will be selected and analyzed. The new CGRA will be optimized for these kernels.
Next, the parameterized HiPReP architecture, i.e. the design of the hardware, will be determined and a simulation model in the SystemC language will be implemented. For efficiently using the extension by FPUs, novel communication and synchronization mechanisms have to be devised, and the integration of a HiPReP module in the memory hierarchy of a HPC system must be investigated.
In parallel to the hardware development, a high-level language compiler prototype will be implemented for HPC applications on HiPReP. A compiler is required since the practical use of a processor can only be evaluated with a corresponding compiler. For this, suitable compilation, scheduling and placement algorithms will be developed.
Finally, a design space exploration will be performed in the evaluation phase of this project. Therefore, the benchmark kernel executions will be simulated on the HiPReP processor, and an optimal point in the design space will be determined. For this design, the area, frequency and power consumption of a chip implementation will be estimated.
- Ph. Käsgen, M. Weinhardt, Chr. Hochberger: A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications, Proc. of the 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2018), Cancun, Mexiko, Dec. 2018
- Ph. Käsgen and M. Weinhardt: Using Template Metaprogramming for Hardware Description, Proc. 21. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen", Universität Tübingen, März 2018
- Käsgen P.S., Weinhardt M., Hochberger C. (2019) Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements. In: Schoeberl M., Hochberger C., Uhrig S., Brehm J., Pionteck T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science, vol 11479. Springer, Cham, https://doi.org/10.1007/978-3-030-18656-2_12
- Fabian Brisch
Former Student Assistants
- Winfried Krafft
- Danish Saadi
- Benedict Scheidl
- Rainer Höckmann